Versatile Processor Design for Efficiency and High Performance

We present new architectural concepts for uniprocessor designs that conform to the data-driven computation paradigm. Usage of our D-CPU (Data-Driven processor) follows the natural flow of programs, minimizes the number of redundant operations, lowers the hardware cost, and reduces the power consumption. Instead of giving the CPU the privileged right of deciding what instructions to fetch in each cycle, instructions are entering the CPU when they are ready to execute or when all their operand(s) are to be available within a few clock cycles. Thus, the application-knowledgeable algorithm, rather than the application-ignorant CPU, is in control. It results in outstanding performance and elimination of large numbers of redundant operations that plague current processor designs. The latter, conventional CPUs are characterized by numerous redundant operations, such as the first memory cycle in instruction fetching that is part of any instruction cycle, and instruction and data prefetchings for instructions that are not always needed. A comparative analysis of our design with conventional designs proves that it is capable of better performance, simpler programming, and high efficiency.